Power Efficient System and A/D Converter Design for Ultra-Wideband Radio

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Ultra-Wideband (UWB) technology has been approved by the FCC in 2002 and has since drawn considerable attention for a variety of applications, including communications , imaging, surveillance, and locationing. One of the most attractive applications is for the indoor communication system which is allowed to operate in the frequency band from 3.1 to 10.6 GHz. The interest in these indoor systems extends from high-speed, short-range systems to low data rate communications and precision ranging, as seen in the standardization efforts of IEEE 802.15.3a/4a. The data rate of interest scales from 10's Kbps to 100's Mbps. Regardless of application, it is very crucial to design with low cost and low power; especially as many of these applications intend to deploy a large volume of inexpensive UWB mobile devices that must operate with the longest possible battery life. 2 This thesis proposes both system and circuit solutions intended for minimal UWB implementation cost. At the system level, an impulse radio architecture utilizing a sub-sampling analog front-end along with digital complex signal processing is proposed to allow a low complexity implementation of a 3.1-10.6 GHz Ultra-Wideband radio. The proposed system modulates information onto passband pulses using a pulser and antenna, and the receiver front-end down-converts the signal frequency via sub-sampling, thus, requiring substantially less hardware than the existing direct conversion approach. After analog-to-digital converter (ADC), the signal is projected into complex signal domain to perform matched filtering to not only mitigate the timing sensitivity induced by analog circuit impairment, but also extract the fine time resolution provided by the wideband nature of a UWB signal. Based on this transceiver architecture, the most challenging circuit block was found to be the high-speed (GHz) ADC, requiring to sub-sample the RF frequencies. As a result, an asynchronous analog-to-digital converter (ADC) based on successive approximation is introduced to provide a high speed (600-MS/sec) and medium resolution (6 bits) conversion. A high input bandwidth (>4 GHz) was achieved which allows its use in RF sub-sampling applications. By using asynchronous processing …